The present invention relates to a comparator circuit employed in a flash A/D converter.
In converting an analog signal into a digital signal at a high speed, the conventional flash A/D converter is used. The basic configuration of the flash A/D converter is commonly known and described in U.S. Pat. No. 4,276,543. In the flash A/D converter, it is necessary to compare an analog signal with a number of reference voltages by using the same number of comparator circuits. Thus, the performance of the flash A/D converter is affected by the performance of the comparator circuits.
FIG. 3 is diagram showing a comparator circuit employed in the A/D converter disclosed in the U.S. patent mentioned above.
An analog input terminal 104 is a terminal common to all the comparator circuits 102. An analog input signal Vin to be converted into a digital signal is supplied to the analog input terminal 104. A reference voltage Vref is supplied to each of the comparator circuits 102. The reference voltage Vref that varies from comparator circuit 102 to comparator circuit 102 is supplied to a reference voltage 106. A latch (or a master latch) circuit 108 at the first stage of the comparator circuit 102 is directly connected to the analog input terminal 104 for receiving the analog input signal Vin and a reference-voltage terminal 106 for receiving the reference voltage Vref. Thus, switching noises attributed to sampling clock signals CLK and CLKxe2x80x2 are returned to the input side in a phenomenon known as a xe2x80x98kickbackxe2x80x99, causing conversion noises to increase.
In order to avoid this phenomenon, there has been proposed a comparator circuit 118 having a configuration in which, as shown in FIG. 4, a pre-amplifier is provided as a comparator stage 112 in front of a master latch 110, the comparator stage 112 and the latch stage 110 are separated from each other, a power-supply line AVCC in the comparator stage 112 is separated from a power-supply line DVCC in the latch stage 110, a ground line AGND in the comparator stage 112 is separated from a ground line DGND in the latch stage 110, and the comparator stage 112 and the latch stage 110 are connected to each other only by an emitter-follower comprising transistors 114 and 116. For more information on the comparator circuit 118, refer to a document authored by Yukio Akazawa, Atushi Iwata, Tsutomu Wakimoto, Tshuomu Kamato, Hiroaki Nakamura and Hyoh Ikawa entitled xe2x80x9cA 400 MSPS 8b Flash AD Conversion LSIxe2x80x9d of ISSCC Digest of Technical Papers, pp. 98-99, issued in February 1987. At the present time, such a configuration is adopted as a standard of comparator circuits employed in flash A/D converters.
In addition, since the comparator stage 112 and the latch stage 110 are separated from each other in this configuration, the range of the reference voltages Vref in the comparator circuits 112 can be widened. Furthermore, at the latch stage 110, the number of transistors provided in series between the power-supply line DVCC and the ground line DGND, that is, the number of vertically connected transistors, is small. A small number of such transistors is advantageous for efforts to reduce the level of the power supply.
The main characteristics of the flash A/D converter include an input-distortion-vs-frequency characteristic. FIG. 5 is a diagram showing a graph representing a typical result of a measurement of the input-distortion-vs-frequency characteristic in the conventional flash A/D converter. In the figure, the horizontal axis represents the frequency and the vertical axis represents an SNDR, which is an abbreviation of Signal to (Noise+Distortion) Ratio.
The graph shown in FIG. 5 is obtained by supplying a voltage sinusoidal over almost its full range to a 6-bit A/D converter and applying FFT processing to the output of the A/D converter. The output of the A/D converter includes not only analog distortions but also quantization distortions. A signal including distortions of both types is evaluated by using the SNDR.
As shown in FIG. 5, as the frequency increases, the SNDR decreases. A main cause of the decrease in SNDR is the increase in low-order harmonic components with frequencies of two to three times the frequency of the input signal. This cause is identified from results of a frequency analysis carried out on the signal output by the A/D converter.
With regard to a mechanism in which such a low-order harmonic distortion (which is referred to simply as a harmonic distortion) is generated, there are many causes of the distortion. In addition, the causes are related to each other so that it is difficult to analyze the causes. As a result, the causes are not well identified so far.
A typical analysis of harmonic distortions is disclosed in xe2x80x9cIntegrated Analog-to-Digital and Digital-to-Analog Convertersxe2x80x9d by Rudy van de Plassche, a publication of Kluwer Academic Publishers, in 1994, on page 189 to 203. FIG. 6 is a diagram showing a model of the comparator circuit in relationship to the analysis of harmonic distortions and is also shown on page 191 of this reference. In accordance with this model, the comparator circuit comprises an amplitude limiter 120 and a primary delay system 122. This model can be used for explaining relatively well the phenomenon in a qualitative manner. Since the latch stage is not taken into consideration, however, the model is too simple to represent the actual comparator circuit.
It is thus an object of the present invention addressing the problems described above to provide a comparator circuit introducing only a few variations in sampling delay and capable of suppressing harmonic distortions in a flash A/D converter or the like.
In order to achieve the object described above, the present invention provides a comparator circuit that includes a comparator stage including a first differential amplifier circuit; a latch stage for fetching signals output by the comparator stage and holding as well as outputting level signals for the fetched signals synchronously with sampling clock signals; and a feedback circuit for feeding back signals output by the latch stage to the comparator stage as negative feedback signals; wherein the latch stage includes a second differential amplifier circuit for inputting the signals output by the comparator stage; and a latch main unit for holding signals output by the second differential amplifier circuit; and the second differential amplifier circuit and the latch main unit work alternately in synchronization with the sampling clock signals.
In the case of an input signal with a high through-rate, the comparator stage supplies differential signals each having a sufficient amplitude to the second differential amplifier circuit serving as a transfer unit of the latch stage as described above. Thus, even while the second differential amplifier circuit is transiting to a non-operative state to result in a low sensitivity, the second differential amplifier circuit is capable of driving and inverting the latch main unit. As a result, the sampling delay becomes shorter.
For a comparator circuit implemented by this embodiment, however, the signals output by the second differential amplifier circuit each have sufficient amplitude at that time. Thus, the signals output by the comparator stage are strongly suppressed by a negative feedback effect provided by the feedback circuit and, as a result, signals input to the second differential amplifier circuit become weaker. In consequence, the second differential amplifier circuit is no longer capable of inverting the latch main unit unless the timing is a timing providing a sensitivity higher than the conventional comparator circuit. As a result, the sampling delay becomes longer.
In the case of an input signal with a low through-rate, on the other hand, the comparator stage supplies differential signals each having an insufficient amplitude to the second differential amplifier circuit of the latch stage as described above. Thus, if the second differential amplifier circuit is transiting to a non-operative state to result in a low sensitivity, the second differential amplifier circuit is not capable of driving the latch main unit. As a result, the sampling delay is longer.
In the case of the comparator circuit implemented by this embodiment, however, the signals output by the second differential amplifier circuit each have a small amplitude at that time. Thus, the signals output by the comparator stage are not so suppressed by the negative feedback effect provided by the feedback circuit and, as a result, signals input to the second differential amplifier circuit become stronger. In consequence, the second differential amplifier circuit is capable of inverting the latch main unit even if the timing is a timing providing a sensitivity lower than the conventional comparator circuit. As a result, the sampling delay becomes shorter.
As a result, in the case of the comparator circuit implemented by this embodiment, as a whole, variations in sampling delay are suppressed.
In addition, in a flash A/D converter employing a comparator circuit provided by the present invention, variations in sampling delay in the comparator circuit are small, resulting in suppressed harmonic distortions.